Download Section (Publicly available):

Cite as:
A. Sengupta et al "AspireHLS Tool: An HLS Tool/Framework for Data-Intensive Applications", Indian Institute of Technology Indore, Publicly released in June 2026, Available at: https://www.anirban-sengupta.com/AspireHLS_HLS_Tool.php

Disclaimer: Please cite/reference the tool during usage, as our tool algorithms/materials contains copyrighted materials from IEEE/IET

The GUI of the compiler-driven HLS HLT Tool package integrated within the AspireHLS Tool, is shown below:








Summary : It describes our 'AspireHLS' tool that is an HLS tool/framework that generates RTL datapath (as hypergraph) from input intermediate representation (IR) as DFG (generated from its high level code such as C).

The HLS Benchmarks in the form of high level description (transfer function) and it associated intermediate representation (IR) as CDFG/DFG is also publicly available here: HLS Benchmarks. The relevant research paper citations, where the high level description (transfer function) and it associated intermediate representation (IR) as CDFG/DFG is described, is also present in the PDF file.

Details of the Tool: The AspireHLS Tool is designed in a modular fashion, implemented as three modules. The three major modules are:

(a) HLS Front End: This is performed using our HLS HLT Tool. The Tool requires java development kit (jdk 17) installed for executing the HLS HLT tool. The HLS HLT Tool converts a raw DFG into a processed/transformed DFG (i.e. intermediate representation (IR)) using a set of structural compiler transformation techniques such as THT, LU, ROE (adopted from the references below). The tutorial for HLS HLT Tool (Tutorial_HLS_HLT_Tool.pdf) can be accessed below, as well as available in the Github link.
Note: The jdk 17 can be downloaded and installed from the following: JDK 17

(b) HLS Middle End: This is performed using our PSO-DSE tool that exploits particle swarm optimization (PSO) based design space exploration process for exploring optimized hardware IP design architecture based on area-latency tradeoff. The tool requires java development kit (jdk) installed for executing the tool.

(c) HLS Back End: This module is responsible for accepting the processed DFG from HLS HLT tool and explored architecture from PSO-DSE tool (based on area-latency tradeoff)/or directly feeding resource constraints for performing scheduling, resource allocation, binding, register allocation and RTL datapath generation etc.

Access Tool Download

Access Tool Tutorial

View the Hi-Res Tool GUI image

Readme_IR_HLS Tool - "How to create the DFG Intermediate Representation (IR) input file format for the tool"


Relevant Publications:
-- A. Sengupta, D. Roy "Protecting an Intellectual Property Core during Architectural Synthesis using High-Level Transformation Based Obfuscation" IET Electronics Letters, Volume: 53, Issue: 13, June 2017, pp. 849 - 851
-- A. Sengupta, V. Kumar Mishra, "Swarm Intelligence Driven Simultaneous Adaptive Exploration of Datapath and Loop Unrolling Factor during Area-Performance Tradeoff ", Proceedings of 13th IEEE Computer Society Annual International Symposium on VLSI (ISVLSI), Florida, USA, July 2014, pp. 106 112
-- A. Sengupta, D. Roy et al. "DSP Design Protection in CE through Algorithmic Transformation Based Structural Obfuscation", IEEE Transactions on Consumer Electronics, Volume 63, Issue 4, November 2017, pp: 467 - 476
-- A. Sengupta et al. "High-Level Synthesis of Digital Circuits in the Nanoscale, Mobile Electronics Era", IET Book: Nano-CMOS and Post-CMOS Electronics: Circuits and Design, Book Chapter, e-ISBN: 9781785610004, pp: 219 - 261
-- A. Sengupta et al., "A High Level Synthesis design flow with a novel approach for Efficient Design Space Exploration in case of multi parametric optimization objective", Elsevier Microelectronics Reliability, Vol. 50 (3), 2010, pp. 424-437
-- A. Sengupta, S. Bhadauria et al. "Embedding Low Cost Optimal Watermark During High Level Synthesis for Reusable IP Core Protection", Proc. of 48th IEEE Int'l Symposium on Circuits & Systems (ISCAS), Montreal, May 2016, pp. 974 - 977.

---