Industry usage, industry patents and industry product developments using Dr. Sengupta’s technologies

a) 1st Technology of Dr. Anirban Sengupta -: DSP system architecture optimization using Design Space Exploration
(First Inventor: Dr. Anirban Sengupta)

2 US Patents (US Patent 8,397,204, US 8,826,199 B2)
2 Canadian Patents (CA2726091A1, CA2741253A1)

Industries that used Dr. Sengupta’s innovation: MaRS Innovation, (Toronto, Canada), Calypto (USA), Bluespec (USA), BEECube (USA), Huawei (Canada).

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Some examples of industry usage, industry patents and industry product developments using Dr. Sengupta’s patents include:

• US Patent 9,529,951, 2016 for “Synthesis tuning system for VLSI design optimization” by International Business Machines Corp,
• US Patent US9111059B2 for “System of dynamic management of hardware resources in reconfigurable framework” by Science and Technology Corporation University of New Mexico,
• US Patent 9,429,921, 2016 for system for “energy management control” by Siemens AG,
• US Patent 8,826,199, 2014 for “system architecture optimization” by Ryerson University, Canada,
• US Patent 9,910,949, 2018 for “Synthesis tuning system for VLSI design optimization” by IBM Corporation,
• US Patent 9,697,028, 2017 for “placement of guest virtual machines on distributed and/or virtualized computer system within communications latency constraints” by Amazon Technologies Inc,
• US9542198B2 for “methods for dynamic management of hardware resources” by Science and Technology Corporation University of New Mexico,
• US9697018B2 for “Synthesizing inputs to preserve functionality”- International Business Machines Corp,
• US9337845B2 for “Solving constraint satisfaction problems using a field programmable gate array” by International Business Machines Corp
• US20130080140A1 for “designing a requirements framework for computing devices” by MathWorks Inc

b) Technology: Detective and Preventive Control for Hardware Security/IP Protection of DSP cores
Patents:
2 Indian Patents (Patent ref. 4466/MUM/2015, Patent ref. 1666/MUM/2015)

Technical publications available publicly in IEEE that are cited and used by industry:

• Anirban Sengupta, Dipanjan Roy "Low-Overhead Highly Robust Embedded RTL Signature for DSP Core Protection: New Paradigm for Smart CE Design", Proceedings of 37th IEEE International Conference on Consumer Electronics (ICCE), Las Vegas, USA, Jan 2019, pp. 1- 6 (Best paper Award out of 350 submissions)
• Dipanjan Roy, Anirban Sengupta "Multi-level Watermark for Protecting DSP Kernel used in CE Systems", IEEE Consumer Electronics Magazine, Volume: 8 , Issue: 2 , March 2019, pp. 100 – 102
• Anirban Sengupta, Saumya Bhadauria, Saraju P Mohanty "TL-HLS: Methodology for Low Cost Hardware Trojan Security Aware Scheduling with Optimal Loop Unrolling Factor during High Level Synthesis", IEEE Transactions on Computer Aided Design of Integrated Circuits & Systems (TCAD), Volume: 36, Issue: 4, April 2017, pp. 655 – 668
• Anirban Sengupta, Dipanjan Roy, Saraju P Mohanty, "Triple-Phase Watermarking for Reusable IP Core Protection during Architecture Synthesis", IEEE Transactions on Computer Aided Design of Integrated Circuits & Systems (TCAD), Volume: 37, Issue: 4, April 2018, pp. 742 - 755
• Anirban Sengupta, Saumya Bhadauria, "Exploring Low Cost Optimal Watermark for Reusable IP Cores during High Level Synthesis", IEEE Access Journal, Invited paper, Volume:4, Issue: 99, pp. 2198 - 2215, May 2016
• Anirban Sengupta, Saumya Bhadauria, Saraju Mohanty "Embedding Low Cost Optimal Watermark During High Level Synthesis for Reusable IP Core Protection", Proc. of 48th IEEE Int'l Symposium on Circuits & Systems (ISCAS), Montreal, May 2016, pp. 974 - 977
• Anirban Sengupta, Saumya Bhadauria "Untrusted Third Party Digital IP cores: Power-Delay Trade-off Driven Exploration of Hardware Trojan Secured Datapath during High Level Synthesis", 25th IEEE/ACM Great Lake Symposium on VLSI (GLSVLSI), Pennsylvania, May 2015, pp. 167 - 172

1st Technology of Dr. Anirban Sengupta - Industry that used Dr. Sengupta’s innovation on Detective and Preventive Control for Hardware Security/IP Protection of DSP cores (Watermarking based security technology): VividSparks IT Solutions Pvt Ltd and had been put into the market (distributors of the company in Germany, China, United Kingdom, France Russia and South Korea). Few of the products where Dr. Sengupta’s publicly available technical contributions (hardware security technologies) have been integrated are SupersoniK co-processor based on an array of POSIT arithmetic units and RISC-V Pulpino with POSIT co-processors (TEZ processor) which are deployed in high performance computing applications, graphic computing (GPUs), artificial intelligence and electronic control unit of smart cars.

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2nd Technology of Dr. Anirban Sengupta -Industry that used Dr. Sengupta’s innovation on Detective and Preventive Control for Hardware Security/IP Protection of DSP cores (Trojan secured IP core technology): VividSparks IT Solutions Pvt Ltd where CAD tool was developed for commercialization and used in FPGA/SoC products.

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