si Prof./Dr. Anirban Sengupta, Fellow IET, Fellow BCS (UK), Fellow IETE, Professor, Computer Science and Engineering, Indian Institute of Technology (IIT) Indore

Research Publications: 243 Home

Breakup:
Peer-reviewed Journals/Book/Patents/Invited Book Chapters: 155
Peer-reviewed /Conference publications: 78
Thesis/Technology transfer report: 10

    BOOKS

  1. Anirban Sengupta "Secured Hardware Accelerators for DSP and Image Processing Applications", The Institute of Engineering and Technology (IET), Jan 2021, Print: 978-1-83953-306-8, eBook: 978-1-83953-307-5
  2. Anirban Sengupta "Frontiers in Securing IP Cores - Forensic detective control and obfuscation techniques", The Institute of Engineering and Technology (IET), 2020, ISBN-10: 1-83953-031-6, ISBN-13: 978-1-83953-031-9
  3. Anirban Sengupta, Saraju P. Mohanty "IP Core Protection and Hardware-Assisted Security for Consumer Electronics", The Institute of Engineering and Technology (IET), 2019, Book ISBN: 978-1-78561-799-7, e-ISBN: 978-1-78561-800-0
  4. Anirban Sengupta, Sudeb Dasgupta, Virendra Singh, Rohit Sharma, SK Vishvakarma "VLSI Design and Test", Springer Nature - Communications in Computer and Information Science, Vol. 1066, 2019, Book ISBN: 978-981-329-767-8

    5. IET BOOK CHAPTERS

  5. Anirban Sengupta "Introduction: Secured and optimized hardware accelerators for DSP and image processing applications", IET Book "Secured Hardware Accelerators for DSP and Image processing applications", 2021, Print: 978-1-83953-306-8, eBook: 978-1-83953-307-5
  6. Anirban Sengupta "Cryptography driven IP steganography for DSP Hardware Accelerators", IET Book "Secured Hardware Accelerators for DSP and Image processing applications", 2021, Print: 978-1-83953-306-8, eBook: 978-1-83953-307-5
  7. Anirban Sengupta "Double Line of Defence to Secure JPEG Codec Hardware for Medical Imaging Systems", IET Book "Secured Hardware Accelerators for DSP and Image processing applications", 2021, Print: 978-1-83953-306-8, eBook: 978-1-83953-307-5
  8. Anirban Sengupta "Multimodal Hardware Accelerators for Image Processing Filters", IET Book "Secured Hardware Accelerators for DSP and Image processing applications", 2021, Print: 978-1-83953-306-8, eBook: 978-1-83953-307-5
  9. Anirban Sengupta "Integrating Multi-key based Structural Obfuscation and Low-level Watermarking for Double Line of Defence of DSP Hardware Accelerators", IET Book "Secured Hardware Accelerators for DSP and Image processing applications", 2021, Print: 978-1-83953-306-8, eBook: 978-1-83953-307-5
  10. Anirban Sengupta "Fingerprint Biometric for Securing Hardware Accelerators", IET Book "Secured Hardware Accelerators for DSP and Image processing applications", 2021, Print: 978-1-83953-306-8, eBook: 978-1-83953-307-5
  11. Anirban Sengupta "Key-triggered Hash-chaining based Encoded Hardware Steganography for Securing DSP Hardware Accelerators", IET Book "Secured Hardware Accelerators for DSP and Image processing applications", 2021, Print: 978-1-83953-306-8, eBook: 978-1-83953-307-5
  12. Anirban Sengupta "Designing Secured N-point DFT Hardware Accelerator using Obfuscation and Steganography", IET Book "Secured Hardware Accelerators for DSP and Image processing applications", 2021, Print: 978-1-83953-306-8, eBook: 978-1-83953-307-5
  13. Anirban Sengupta "Structural transformation and obfuscation frameworks for Data-intensive IPs", IET Book "Secured Hardware Accelerators for DSP and Image processing applications", 2021, Print: 978-1-83953-306-8, eBook: 978-1-83953-307-5
  14. Anirban Sengupta "Forensic Detective Control using Hardware Steganography for IP Core Protection", IET Book "Frontiers in Securing Hardware IP Cores: Forensic detective control and obfuscation techniques", 2020, ISBN: 978-1-83953-031-9/978-1-83953-032-6
  15. Anirban Sengupta "Forensic Detective Control using Digital Signature based Watermark for IP Core Protection", IET Book "Frontiers in Securing Hardware IP Cores: Forensic detective control and obfuscation techniques", 2020, ISBN: 978-1-83953-031-9/978-1-83953-032-6
  16. Anirban Sengupta "Multi-phase Obfuscation for Fault-secured DSP circuits", IET Book "Frontiers in Securing Hardware IP Cores: Forensic detective control and obfuscation techniques", 2020, ISBN: 978-1-83953-031-9/978-1-83953-032-6
  17. Anirban Sengupta Protection of Fault Secured IP Core using Digital Signature based Watermark", IET Book "Frontiers in Securing Hardware IP Cores: Forensic detective control and obfuscation techniques", 2020, ISBN: 978-1-83953-031-9/978-1-83953-032-6
  18. Anirban Sengupta "Protecting Right of an IP Buyer using Cryptosystem based Multi-variable Fingerprinting", IET Book "Frontiers in Securing Hardware IP Cores: Forensic detective control and obfuscation techniques", 2020, ISBN: 978-1-83953-031-9/978-1-83953-032-6
  19. Anirban Sengupta "Multi-Level Watermark for IP Protection", IET Book "Frontiers in Securing Hardware IP Cores: Forensic detective control and obfuscation techniques" , 2020, ISBN: 978-1-83953-031-9/978-1-83953-032-6
  20. Anirban Sengupta, Mahendra Rathor "Security of Functionally Obfuscated DSP cores", IET Book "Frontiers in Securing Hardware IP Cores: Forensic detective control and obfuscation techniques", 2020, ISBN: 978-1-83953-031-9/978-1-83953-032-6
  21. Anirban Sengupta, Mahendra Rathor "Hologram based Structural Obfuscation for DSP Cores", IET Book "Frontiers in Securing Hardware IP Cores: Forensic detective control and obfuscation techniques", 2020, ISBN: 978-1-83953-031-9/978-1-83953-032-6
  22. Anirban Sengupta "Introduction to Hardware (IP) Security: Forensic Detective Control and Obfuscation of DSP cores", IET Book "Frontiers in Securing Hardware IP Cores: Forensic detective control and obfuscation techniques", 2020, ISBN: 978-1-83953-031-9/978-1-83953-032-6
  23. Anirban Sengupta, Saraju Mohanty, "Introduction to IP Core Protection and Hardware-Assisted Security of Consumer Electronics", IET Book: IP Core Protection and Hardware-Assisted Security for Consumer Electronics, 2019, Book ISBN: 978-1-78561-799-7, e-ISBN: 978-1-78561-800-0.
  24. Saraju Mohanty, Anirban Sengupta "Security in Consumer Electronics and Internet of Things (IoT)", IET, 2019, Book ISBN: 978-1-78561-799-7, e-ISBN: 978-1-78561-800-0.
  25. Anirban Sengupta, Saraju Mohanty, "Trojan Security Aware DSP IP Core and Integrated Circuits", IET Book: IP Core Protection and Hardware-Assisted Security for Consumer Electronics, 2019, Book ISBN: 978-1-78561-799-7, e-ISBN: 978-1-78561-800-0.
  26. Anirban Sengupta, Saraju Mohanty, "IP Core and Integrated Circuit Protection using Robust Watermarking", IET Book: IP Core Protection and Hardware-Assisted Security for Consumer Electronics, 2019, Book ISBN: 978-1-78561-799-7, e-ISBN: 978-1-78561-800-0.
  27. Anirban Sengupta, Saraju Mohanty, "Symmetrical Protection of DSP IP Core and Integrated Circuits using Fingerprinting and Watermarking", IET Book: IP Core Protection and Hardware-Assisted Security for Consumer Electronics, 2019, Book ISBN: 978-1-78561-799-7, e-ISBN: 978-1-78561-800-0.
  28. Anirban Sengupta, Saraju Mohanty, "Computational Forensic Engineering for Resolving Ownership Conflict of DSP IP Core", IET, 2019, Book ISBN: 978-1-78561-799-7, e-ISBN: 978-1-78561-800-0.
  29. Anirban Sengupta, Saraju Mohanty, "Structural Obfuscation of DSP Cores used in CE Devices", IET Book: IP Core Protection and Hardware-Assisted Security for Consumer Electronics, 2019, Book ISBN: 978-1-78561-799-7, e-ISBN: 978-1-78561-800-0.
  30. Anirban Sengupta, Saraju Mohanty, "Functional Obfuscation of DSP Cores used in CE Devices", IET Book: IP Core Protection and Hardware-Assisted Security for Consumer Electronics, 2019, Book ISBN: 978-1-78561-799-7, e-ISBN: 978-1-78561-800-0.
  31. Anirban Sengupta, Saraju Mohanty, "Obfuscation of JPEG CODEC IP Core for CE Devices", IET Book: IP Core Protection and Hardware-Assisted Security for Consumer Electronics, 2019, Book ISBN: 978-1-78561-799-7, e-ISBN: 978-1-78561-800-0.
  32. Anirban Sengupta, Saraju Mohanty, "Advanced Encryption Standard (AES) and its Hardware Watermarking for Ownership Protection", IET Book: IP Core Protection and Hardware-Assisted Security for Consumer Electronics, 2019, Book ISBN: 978-1-78561-799-7, e-ISBN: 978-1-78561-800-0.
  33. Anirban Sengupta "HAAR Computation Reduction Functions", IET Book: IP Core Protection and Hardware-Assisted Security for Consumer Electronics, 2019, pp. 447 - 457, ISBN: 978-1-78561-799-7, e-ISBN: 978-1-78561-800-0.
  34. Anirban Sengupta "Transfer functions and control data flow graph of DSP cores", IET Book: IP Core Protection and Hardware-Assisted Security for Consumer Electronics, 2019, pp. 484 - 491, ISBN: 978-1-78561-799-7, e-ISBN: 978-1-78561-800-0.
  35. Anirban Sengupta "Controller design details for JPEG codec IP core", IET Book: IP Core Protection and Hardware-Assisted Security for Consumer Electronics, 2019, pp. 459 - 483, ISBN: 978-1-78561-799-7, e-ISBN: 978-1-78561-800-0.
  36. Saraju Mohanty, Anirban Sengupta, "Hardware Approaches for Media and Information Protection and Authentication", IET Book: IP Core Protection and Hardware-Assisted Security for Consumer Electronics, 2019, Book ISBN: 978-1-78561-799-7, e-ISBN: 978-1-78561-800-0.
  37. Saraju Mohanty, Anirban Sengupta, "Physical Unclonable Functions (PUFs)", IET Book: IP Core Protection and Hardware-Assisted Security for Consumer Electronics, 2019, Book ISBN: 978-1-78561-799-7, e-ISBN: 978-1-78561-800-0.
  38. Anirban Sengupta, Mahendra Rathor, "Design Space Exploration of DSP hardware using Bacterial Foraginga and Particle Swarm Optimization Algorithm for Power/Area-Delay Tradeoff", IET Book, Low Power Nanoscale IC Design, Invited Book Chapter, 2020.
  39. Anirban Sengupta, Deepak Kachave, "Transient Fault-Tolerant Datapath during High Level Synthesis for DSP Cores: Data Intensive Applications", IET Book: VLSI and Post-CMOS Devices, Circuits and Modelling, Invited Book Chapter, 2018.
  40. Anirban Sengupta, Saraju P.Mohanty "High-Level Synthesis of Digital Circuits in the Nanoscale, Mobile Electronics Era", IET Book: Nano-CMOS and Post-CMOS Electronics: Circuits and Design, (Eds: Saraju P Mohanty& Ashok Srivastava), Invited Book Chapter, e-ISBN: 9781785610004, pp: 219 - 261, June 2016.

    41. Springer/CRC Book Chapters


  41. Anirban Sengupta "Secured Integrated Circuit (IC/IP) Design Flow", CRC Book "Nanoelectronics for Next-generation Integrated Circuits", 2021, Invited Book Chapter
  42. Anirban Sengupta, Rahul Chaurasia "Hardware IP Cores for Image Processing Functions", IOP Book "Hardware IP Cores for Image Processing Functions", 2021, Invited Book Chapter
  43. Anirban Sengupta, Dipanjan Roy "Securing dedicated DSP Coprocessors (Hardware IP) using Structural Obfuscation for IoT-oriented platforms", CRC Book, Taylor & Francis "Security of Internet of Things Nodes Challenges, Attacks, and Countermeasures", 2020, Invited Chapter (Eds.Chinmay Chakrabarty, Sree Ranjani Rajendran, Rajat Subhra Chakraborty, Muhammad Habib ur Rehman)
  44. Anirban Sengupta, Mahendra Rathor "Hardware (IP) Watermarking during Behavioural Synthesis", Springer Book "Behavioral Synthesis for Hardware Security", 2020, Invited Chapter (Eds.Srinivas Katkoori, Sheikh Ariful Islam)
  45. Anirban Sengupta, Dipanjan Roy "Low Cost Dual-Phase Watermark for Protecting CE Devices in IoT Framework", Springer Book: Security and Fault Tolerance in Internet of Things, Invited Book Chapter, Dec 2018, pp. 21 - 41, Print ISBN 978-3-030-02806-0 (Eds: Chakraborty R., Mathew J., Vasilakos A.).
  46. Anirban Sengupta, "Design Space Exploration of Datapath (Architecture) in High Level Synthesis for Computation Intensive Applications", Springer Book volume: Application of Evolutionary Algorithms for Multi-Objective Optimization in VLSI and Embedded Systems, Print ISBN: 978-81-322-1957-6, August 2014, pp. 93 - 111.
  47. Anirban Sengupta, "Design Flow from Algorithm To RTL using Evolutionary Exploration Approach", Springer Book volume: Application of Evolutionary Algorithms for Multi-Objective Optimization in VLSI and Embedded Systems, Print ISBN: 978-81-322-1957-6, August 2014, pp. 113 - 123.

    48. IEEE Transactions/Journals

  48. Anirban Sengupta, Rahul Chaurasia, Tarun Reddy "Contact-less Palmprint Biometric for Securing DSP Coprocessors used in CE systems", IEEE Transactions on Consumer Electronics (TCE) , Accepted, August 2021
  49. Anirban Sengupta, Mahendra Rathor "Facial Biometric for Securing Hardware Accelerators", IEEE Transactions on Very Large Scale Integration Systems (TVLSI) , Volume: 29, Issue: 1, Jan. 2021, pp. 112 - 123
  50. Anirban Sengupta, Mahendra Rathor "Obfuscated Hardware Accelerators for Image Processing Filters - Application Specific and Functionally Reconfigurable Processors", IEEE Transactions on Consumer Electronics (TCE) , Volume: 66, Issue: 4, Nov 2020, pp. 386-395
  51. Anirban Sengupta, Mahendra Rathor "Securing Hardware Accelerators for CE Systems using Biometric Fingerprinting", IEEE Transactions on Very Large Scale Integration Systems (TVLSI) , Volume: 28, Issue: 9, Sep 2020, pp. 1979-1992
  52. Anirban Sengupta, Mahendra Rathor "Enhanced Security of DSP circuits using Multi-key based Structural Obfuscation and Physical-level Watermarking for Consumer Electronics systems", IEEE Transactions on Consumer Electronics (TCE) , Volume: 66, Issue:2, May 2020, pp. 163-172
  53. Mahendra Rathor, Anirban Sengupta "IP Core Steganography using Switch based Key-driven Hash-chaining and Encoding for Securing DSP kernels used in CE Systems", IEEE Transactions on Consumer Electronics (TCE) , Volume: 66, Issue: 3, Aug 2020, pp. 251-260.
  54. W Hu, CH Chang, A Sengupta, S Bhunia, R Castner, H Li "An Overview of Hardware Oriented Security andTrust: Threats, Countermeasures and Design Tools", IEEE Transactions on Computer Aided Design of Integrated Circuits & Systems (TCAD), Accepted, Invited Paper, 2021
  55. W Hu, CH Chang, A Sengupta, S Bhunia, R Castner, H Li "Hardware Oriented Security and Trust", IEEE Transactions on Computer Aided Design of Integrated Circuits & Systems (TCAD), 2021
  56. Anirban Sengupta, Mahendra Rathor "IP Core Steganography for Protecting DSP Kernels used in CE Systems", IEEE Transactions on Consumer Electronics (TCE) , Volume: 65 , Issue: 4 , Nov. 2019, pp. 506 - 515
  57. Anirban Sengupta, E. Ranjith Kumar, N. Prajwal Chandra "Embedding Digital Signature using Encrypted-Hashing for Protection of DSP cores in CE", IEEE Transactions on Consumer Electronics (TCE), Volume: 65, Issue:3, Aug 2019, pp. 398 - 407
  58. Anirban Sengupta, Mahendra Rathor "Protecting DSP Kernels using Robust Hologram based Obfuscation", IEEE Transactions on Consumer Electronics (TCE), Volume: 65, Issue: 1, Feb 2019, pp. 99-108
  59. Anirban Sengupta, Dipanjan Roy, Saraju P Mohanty, Peter Corcoran "Low-Cost Obfuscated JPEG CODEC IP Core for Secure CE Hardware", IEEE Transactions on Consumer Electronics, Volume: 64, Issue:3, August 2018, pp:365-374.
  60. Anirban Sengupta, Saraju P Mohanty "Smart Electronic Systems for Consumer Electronics", IEEE Transactions on Consumer Electronics, Accepted, special section, 2019.
  61. Anirban Sengupta, Saraju P Mohanty, Fernando Pescador, Peter Corcoran "Multi-Phase Obfuscation of Fault Secured DSP Designs with Enhanced Security Feature", IEEE Transactions on Consumer Electronics, Volume: 64, Issue:3, August 2018, pp: 356-364.
  62. Anirban Sengupta, Dipanjan Roy, Saraju Mohanty, Peter Corcoran "DSP Design Protection in CE through Algorithmic Transformation Based Structural Obfuscation", IEEE Transactions on Consumer Electronics, Volume 63, Issue 4, November 2017, pp: 467 - 476
  63. Anirban Sengupta, Deepak Kachave, Dipanjan Roy "Low Cost Functional Obfuscation of Reusable IP Cores used in CE Hardware through Robust Locking", IEEE Transactions on Computer Aided Design of Integrated Circuits & Systems (TCAD), Volume: 38, Issue 4, April 2019, pp. 604 - 616
  64. Anirban Sengupta, Dipanjan Roy, Saraju P Mohanty, "Triple-Phase Watermarking for Reusable IP Core Protection during Architecture Synthesis", IEEE Transactions on Computer Aided Design of Integrated Circuits & Systems (TCAD), Volume: 37, Issue: 4, April 2018, pp. 742 - 755
  65. Anirban Sengupta, Deepak Kachave "Spatial and Temporal Redundancy for Transient Fault Tolerant Datapath", IEEE Transactions on Aerospace and Electronic Systems, Volume: 54, Issue:3, June 2018, pp. 1168-1183
  66. Anirban Sengupta, Sandip Kundu "Securing IoT Hardware: Threat models and Reliable, Low-power Design Solutions", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Dec 2017, Volume: 25, Issue:12, pp. 3265 - 3267.
  67. Anirban Sengupta, Saumya Bhadauria, Saraju P Mohanty "TL-HLS: Methodology for Low Cost Hardware Trojan Security Aware Scheduling with Optimal Loop Unrolling Factor during High Level Synthesis", IEEE Transactions on Computer Aided Design of Integrated Circuits & Systems (TCAD), Volume: 36, Issue: 4, 2016, pp. 655 – 668.
  68. Anirban Sengupta, Mahendra Rathor "HLS based IP Protection of Reusable Cores using Biometric Fingerprint", IEEE Letters of the Computer Society (LOCS) , Accepted, 2020.
  69. Anirban Sengupta, Mahendra Rathor "Structural Obfuscation and Crypto-Steganography based Secured JPEG Compression Hardware for Medical Imaging Systems", IEEE Access, Volume: 8, Issue:1, Dec 2020, pp. 6543-6565
  70. Mahendra Rathor, Anirban Sengupta "Design Flow of Secured N-point DFT Application Specific Processor using Obfuscation and Steganography", IEEE Letters of the Computer Society (LOCS) , Volume: 3 , Issue: 1 , June 2020, pp. 13 - 16.
  71. Anirban Sengupta, Mahendra Rathor "Security of Functionally Obfuscated DSP core against Removal Attack using SHA-512 based Key Encryption Hardware", IEEE Access Journal, Volume: 7, Issue:1, 2019, pp. 4598 - 4610
  72. Anirban Sengupta, Mahendra Rathor, Somesh Patil, Naukudkar Gaurav Harishchandra "Securing Hardware Accelerators using Multi-Key based Structural Obfuscation", IEEE Letters of the Computer Society (LOCS) , Volume: 3, Issue:1, June 2020, pp. 21-24.
  73. Mahendra Rathor, Anirban Sengupta "Robust Logic locking for Securing Reusable DSP Cores", IEEE Access Journal, Volume: 7, Aug 2019, pp. 120052 - 120064
  74. Anirban Sengupta, Mahendra Rathor "Crypto based Dual phase Hardware Steganography for Securing IP cores", IEEE Letters of the Computer Society (LOCS) , 2019, Volume 2 , Issue 4, pp. 32-35
  75. Dipanjan Roy, Anirban Sengupta "Multi-level Watermark for Protecting DSP Kernel used in CE Systems", IEEE Consumer Electronics, Volume: 8 , Issue: 2 , March 2019, pp. 100 - 102
  76. Anirban Sengupta,, Deepak Kachave, "Digital Processing Core Performance Degradation Due to Hardware Stress Attacks", IEEE Potential, Volume: 38, Issue: 2, March-April 2019, pp. 39 - 45.
  77. Dipanjan Roy, Anirban Sengupta, Mrinal Kanti Naskar "Signature-Free Watermark for Protecting DSP core used in CE Devices", IEEE Consumer Electronics, Volume 8, Issue 1, Jan 2019, pp. 92 - 94
  78. Anirban Sengupta, Dipanjan Roy, Saraju Mohanty, Peter Corcoran "A Framework for Hardware Efficient Reusable IP Core for Grayscale Image CODEC", IEEE Access Journal, Volume: 6, Issue:1, Dec 2018, pp. 871 - 882
  79. Deepak Kachave, Anirban Sengupta "Fault Tolerant DSP core datapath against Omni-directional spatial impact of SET", IEEE Canadian Journal of Electrical and Computer Engineering, Volume 42, issue 2, Spring 2019, pp. 102 - 107
  80. Anirban Sengupta, Niranjan Ray, "Audio & Video Technologies of Consumer Electronics Devices", IEEE Consumer Electronics, Volume: 7, Issue: 5, Sept. 2018, pp. 26 - 26.
  81. Anirban Sengupta, Saraju P. Mohanty "Editorial: From the Editors Desk", IEEE VLSI Circuits & Systems Letter, Volume 5, Issue 1, Feb 2019, pp. 1.
  82. Anirban Sengupta "Editorial: From the Editors Desk", IEEE VLSI Circuits & Systems Letter, Volume 5, Issue 2, May 2019, pp. 1.
  83. Dipanjan Roy, Anirban Sengupta, "Obfuscated JPEG Image Decompression IP Core for Protecting Against Reverse Engineering", IEEE Consumer Electronics, Volume: 7, Issue: 3, May 2018, pp. 104 - 109
  84. Anirban Sengupta, Dipanjan Roy "Framework for IP based Lossless Image Compression for Camera Systems", IEEE Consumer Electronics, Volume: 7, Issue: 1, pp. 119 - 124, 2018
  85. Deepak Kachave, Anirban Sengupta "Functionally Locked IP Core in CE Hardware for Shielding against Reverse Engineering Attacks", IEEE Consumer Electronics, Volume: 7, Issue: 2, March 2018, pp. 111 - 114
  86. Anirban Sengupta "Editorial: From the Editors Desk", IEEE VLSI Circuits & Systems Letter, Volume 5, Issue 3, Aug 2019, pp. 1.
  87. Anirban Sengupta "Editorial: From the Editors Desk", IEEE VLSI Circuits & Systems Letter, Volume 5, Issue 4, Nov 2019, pp. 1.
  88. Dipanjan Roy Anirban Sengupta, MK Naskar "Optimizing DSP IP Cores using Design Transformation", IEEE Consumer Electronics, Volume: 7 , Issue: 4 , July 2018, pp. 91 - 94
  89. Anirban Sengupta, Saumya Bhadauria, "Exploring Low Cost Optimal Watermark for Reusable IP Cores during High Level Synthesis", IEEE Access Journal, Invited paper, Volume:4, Issue: 99, pp. 2198 - 2215, May 2016 .
  90. Anirban Sengupta, F. Lombardi, S.P Mohanty, M. Zwolinski, "Security and Reliability Aware System Design for Mobile Computing Systems", IEEE Access Journal, Volume: 4, 2016, pp. 2976 - 2980 .
  91. S. P. Mohanty, A. Sengupta, P. Guturu, and E. Kougianos, "Everything You Want to Know About Watermarking: From Paper Marks to Hardware Protection", IEEE Consumer Electronics, Volume 7, Issue 3, July 2017, pp. 83--91.
  92. Anirban Sengupta "Hardware Vulnerabilities and its Effect on CE Devices: Design-for-Security against Trojan", IEEE Consumer Electronics, Volume: 6, Issue: 3, July 2017, pp. 126 - 133.
  93. Anirban Sengupta, Dipanjan Roy "Anti-Piracy aware IP Chipset Design for CE Devices: Robust Watermarking Approach", IEEE Consumer Electronics, Volume: 6, Issue: 2, April 2017, pp. 118 - 124.
  94. Anirban Sengupta, "Hardware Security of CE Devices: Threat Models and Defence against IP Trojans and IP Piracy", IEEE Consumer Electronics, Jan 2017, Volume: 6, Issue: 1 ,pp. 130 - 133.
  95. Anirban Sengupta, Santosh Rathlavat, Mrinal Kanti Naskar "A Firefly Algorithm Approach for Hardware Accelerators in CE Devices", IEEE Consumer Electronics, Volume: 6, Issue: 4, Oct. 2017
  96. Anirban Sengupta "Resilient Soft IP-Core Design Against Terrestrial Transient Faults for CE Products", IEEE Consumer Electronics, Volume: 5, Issue: 4, Oct. 2016, pp. 129 - 131.
  97. Anirban Sengupta, Deepak Kachave "Applying digital forensic for hardware protection : resolving false claim of IP ownership", IEEE VLSI Circuits & Systems Letter, Volume 4, Issue 1, Feb 2018, pp. 10 - 13.
  98. Anirban Sengupta, Saraju P. Mohanty "Editorial: From the Editors Desk", IEEE VLSI Circuits & Systems Letter, Volume 4, Issue 1, Feb 2018, pp. 1.
  99. Anirban Sengupta, "Design Flow of a Digital IC for CE Products", IEEE Consumer Electronics, April 2016,Vol.5, Issue: 2, pp.58 - 62.
  100. Anirban Sengupta "Cognizance on Intellectual Property: A High-Level Perspective", IEEE Consumer Electronics, Vol. 5, Issue 3, pp. 126 - 128, 2016.
  101. Anirban Sengupta "Evolution of IP Design Process in Semiconductor/EDA Industry", IEEE Consumer Electronics, April 2016, Vol.5, Issue: 2, pp.123 - 126.
  102. Anirban Sengupta "Protection of IP-Core Designs for CE Products", IEEE Consumer Electronics, Vol 5, pp. 83- 89, Dec 2015.
  103. Anirban Sengupta, Saraju P. Mohanty "Editorial: From the Editors Desk", IEEE VLSI Circuits & Systems Letter, Volume 4, Issue 2, May 2018, pp. 1.
  104. Anirban Sengupta, Saraju P. Mohanty "Editorial: From the Editors Desk", IEEE VLSI Circuits & Systems Letter, Volume 4, Issue 3, July 2018, pp. 1.
  105. Anirban Sengupta, Saraju P. Mohanty "Editorial: From the Editors Desk", IEEE VLSI Circuits & Systems Letter, Volume 4, Issue 4, Nov 2018, pp. 1.
  106. Anirban Sengupta "Mathematical Models for Latency Estimation of Loop Unrolled and Loop Pipelined CDFGs during High Level Synthesis", IEEE VLSI Circuits & Systems Letter, Volume 2, Issue 2, 2017, pp. 15 - 18.
  107. Saumya Bhadauria, Anirban Sengupta, "Multi-Cycle Single Event Transient Fault Security Aware MO-DSE for Single loop CDFGs in HLS”, IEEE VLSI Circuits & Systems Letter, Vol. 1, Issue 2, Oct 2015, pp. 2-8.
  108. Anirban Sengupta "Protection of Reusable IP core at Architectural Level", IEEE VLSI Circuits & Systems Letter, Vol. 1, Issue 2, Oct 2015, pp. 14 - 17.
  109. Anirban Sengupta, Vipul Kumar Mishra, "A Methodology for Comprehensive Schedule Delay Estimation during Design space Exploration in Architectural Synthesis", IEEE VLSI Circuits & Systems Letter, Volume 1, Issue 1, April 2015, pp. 2 - 8.


    110. IET Journals

  110. Anirban Sengupta "Structurally Obfuscated Custom Processor for Linear Regression based Machine Learning", IET Computers and Digital Techniques, 2021, Invited Paper
  111. Mahendra Rathor, Anirban Sengupta "Low-Cost Robust Anti-Removal Logic for Protecting Functionally Obfuscated DSP core against Removal Attack", IET Electronics Letters, Volume 55, Issue 7, April 2019, pp. 374 – 376
  112. Anirban Sengupta, SP Mohanty, Garrett Rose "Hardware - Assisted Design for Security and Protection of Consumer Electronics", IET Computers and Digital Techniques, Vol. 12 Issue 6, 2018, pp. 249-250
  113. Deepak Kachave, Anirban Sengupta,, Shubha Neema, Panugothu Sri Harsha "Effect of NBTI Stress on DSP cores used in CE Devices: Threat Model and Performance Estimation", IET Computers and Digital Techniques, Volume: 12 , Issue: 6, 2018, pp. 268 - 278
  114. Anirban Sengupta, Dipanjan Roy "Protecting an Intellectual Property Core during Architectural Synthesis using High-Level Transformation Based Obfuscation" IET Electronics Letters, Volume: 53, Issue: 13, June 2017, pp. 849 - 851.
  115. Anirban Sengupta, Deepak Kachave "Particle Swarm Optimisation Driven Low Cost Single Event Transient Fault Secured Design during Architectural Synthesis (Invited Paper)" IET Journal of Engineering, Dec 2017, doi: 10.1049/joe.2016.0378.
  116. Anirban Sengupta, Saumya Bhadauria "IP core Protection of CDFGs using Robust Watermarking during Behavioral Synthesis Based on User Resource Constraint and Loop Unrolling Factor", IET Electronics Letters, Vol. 52 No. 6 pp. 439-441, March 2016.
  117. Anirban Sengupta, Saumya Bhadauria, and Saraju P. Mohanty, "Low Cost Security Aware High Level Synthesis Methodology", IET Journal on Computers & Digital Techniques (CDT), Volume: 11, Issue: 2, 3 2017, pp. 68 - 79.
  118. Anirban Sengupta "Exploration of kc-cycle Transient Fault Secured Datapath and Loop Unrolling Factor for Control Data Flow Graphs during High Level Synthesis", IET Electronics Letters, volume 51, Issue 7, Feb 2015, pp. 562 - 564.
  119. Vipul Kumar Mishra, Anirban Sengupta, "Swarm Inspired Exploration of Architecture and Unrolling Factors for Nested Loop Based Application in Architectural Synthesis", IET Electronics Letters, Volume 51,Issue: 2, Jan 2015, pp. 157 - 159.


    120. Elsevier/Springer/Others Journals

  120. Anirban Sengupta, Deepak Kachave "Forensic Engineering for Resolving Ownership Problem of Reusable IP Core generated during High Level Synthesis", Elsevier Journal on Future Generation Computer Systems, Volume 80, March 2018, Pages 29-46
  121. Anirban Sengupta, Deepak Kachave "Low Cost Fault Tolerance against kc-cycle and km-unit Transient for Loop Based Control Data Flow Graphs during Physically Aware High Level Synthesis", Elsevier Journal on Microelectronics Reliability, Volume 74, July 2017, pp. 88-99.
  122. Dipanjan Roy, Anirban Sengupta "Low Overhead Symmetrical Protection of Reusable IP Core using Robust Fingerprinting and Watermarking during High Level Synthesis", Elsevier Journal on Future Generation Computer Systems, Volume 71, June 2017, pp. 89–101.
  123. Anirban Sengupta, Dipanjan Roy "Automated Low Cost Scheduling Driven Watermarking Methodology for Modern CAD High-Level Synthesis Tools" Elsevier Journal of Advances in Engineering Software, Volume 110, August 2017, pp 26-33.
  124. Deepak Kachave, Anirban Sengupta, “Integrating Physical Level Design and High Level Synthesis for Simultaneous Multi-Cycle Transient and Multiple Transient Fault Resiliency of Application Specific Datapath Processors”, Elsevier Journal on Microelectronics Reliability, Volume 60, Pages 141-152, May 2016.
  125. Anirban Sengupta, Saumya Bhadauria, "Optimized Hardware Design for Trojan Security at Behavioral Level for Loop Based Applications", Elsevier Journal on VLSI Integration, Jan 2016.
  126. Anirban Sengupta, Saumya Bhadauria, Adaptive Bacterial Foraging Driven Datapath Optimization: Exploring Power-Performance Tradeoff in High Level Synthesis, Elsevier Journal on Applied Mathematics & Computation, Vol. 269, pp. 265 - 278 , 2015.
  127. Anirban Sengupta, Saumya Bhadauria, "Bacterial Foraging Driven Exploration of Multi Cycle Fault Tolerant Datapath based on Power-Performance Tradeoff in High Level Synthesis", Elsevier Journal on Expert Systems With Applications, Volume 42, Jan 2015, pp. 4719 - 4732 .
  128. Anirban Sengupta, Reza Sedaghat “Swarm Intelligence Driven Design Space Exploration of Optimal k-Cycle Transient Fault Secured Datapath during High Level Synthesis Based on User Power-Delay Budget", Elsevier Journal on Microelectronics Reliability, Volume 55, Issue 6, May 2015, pp. 990-1004, March 2015.
  129. Anirban Sengupta, Saumya Bhadauria, "Automated Design Space Exploration of Multi-Cycle Transient Fault Detectable Datapath based on Multi-Objective User Constraints for Application Specific Computing", Elsevier Journal on Advances in Engineering Software, Volume 82, April 2015, pp. 14- 24.
  130. Anirban Sengupta, Vipul Kumar Mishra "Automated Exploration of Datapath and Unrolling Factor during Power-Performance Tradeoff in Architectural Synthesis Using Multi-Dimensional PSO Algorithm", Elsevier Journal on Expert Systems With Applications, Volume 41, Issue 10, August 2014,pp. 46914703 .
  131. Vipul Kumar Mishra, Anirban Sengupta, "MO-PSE: Adaptive Multi Objective Particle Swarm Optimization Based Design Space Exploration in Architectural Synthesis for Application Specific Processor Design", Elsevier Journal on Advances in Engineering Software, Volume 67, January 2014, pp. 111124 .
  132. Anirban Sengupta, Saumya Bhadauria "Exploration of Multi-Objective Tradeoff During High Level Synthesis Using Bacterial Chemotaxis and Dispersal", Elsevier Journal on Procedia Computer Science, Sep 2014, Volume. 35, Issue. C, pp. 63 72.
  133. Anirban Sengupta, Reza Sedaghat "Rapid Exploration of Integrated Scheduling and Module Selection in High Level Synthesis for Application Specific Processor Design", Elsevier Journal of Microprocessors and Microsystems", Volume36, Issue 4, Pages 303314, June 2012.
  134. Anirban Sengupta, Reza Sedaghat "A Multi Structure Genetic Algorithm for Integrated Design Space Exploration of Scheduling and Allocation in High Level Synthesis for DSP Kernels", Elsevier Journal of Swarm and Evolutionary Computation, Volume 7, December 2012, Pages 3546.
  135. Anirban Sengupta, Reza Sedaghat, Zhipeng Zeng, "Multi objective Efficient Design Space Exploration and Architectural Synthesis of an Application Specific Processor (ASP)", Elsevier Journal of Microprocessors and Microsystems, Volume 35, Issue 4, June 2011, pp. 392-404.
  136. Anirban Sengupta, Reza Sedaghat, Zhipeng Zeng, "Rapid Design Space Exploration by Hybrid Fuzzy Search Approach for Optimal Architecture determination of Multi Objective Computing Systems", Elsevier Journal of Microelectronics Reliability, Vol. 51, Issue 2, 2011, pp. 502-512.
  137. Anirban Sengupta, Reza Sedaghat, Zhipeng Zeng, "A High Level Synthesis design flow with a novel approach for Efficient Design Space Exploration in case of multi parametric optimization objective", Elsevier Journal of Microelectronics Reliability, Vol. 50, Issue 3, 2010, pp. 424-437.
  138. Anirban Sengupta, VK Mishra. "Simultaneous Exploration of Optimal Datapath and Loop Based High level Transformation during Area-Delay Tradeoff in Architectural Synthesis Using Swarm Intelligence", IOS Press - Journal of Knowledge-Based and Intelligent Engineering Systems, Volume 19, April 2015, pp. 47 - 61.
  139. Anirban Sengupta, Reza Sedaghat, "A High Level Synthesis Design Flow from ESL to RTL with multi-parametric optimization objective", Taylor & Francis, Volume 57, Issue 2, 2011, pp. 169-186.
  140. Anirban Sengupta, Dipanjan Roy "Impact of Hardware Steganography on DSP Core Datapath", Springer, CSI Transactions on ICT, June 2019, pp. 1 - 4, DOI: 10.1007/s40012-019-00247-6.
  141. Anirban Sengupta, Reza Sedaghat, Vipul Kumar Mishra, "Execution Time Area Tradeoff in GA using Residual Load Decoder: Integrated Exploration of Chaining Based Schedule and Allocation in HLS for Hardware Accelerators, Journal of Facta Universitatis: Series Electronics and Energetics, Volume 27, No. 2,pp. 235 249,June 2014.
  142. Reza Sedaghat, Anirban Sengupta, "Rapid Exploration of Cost-Performance Tradeoffs using Dominance Effect during Design of Hardware Accelerators, Journal of Facta Universitatis: Series Electronics and Energetics, Vol. 27, No. 3 , Sep 2014, pp. 317 - 328.
  143. Anirban Sengupta "Temperature-Tolerance Checking System", Electronics For You, Vol. 41, Issue no: 10, pp: 116-117, 2009.
  144. Anirban Sengupta "Automated Alarm Circuits", Electronics For You, Vol.: 41, Issue no: 2, pp: 96-98, 2008.


    145. International Patents

  145. Anirban Sengupta (co-inventor: Reza Sedaghat),"System and Method for Development of System Architecture", US Patent by United Sates Patent and Trademark Office (USPTO), Patent no. US 8,826,199 B2, Sep 2014.
  146. Anirban Sengupta (co-inventor: Reza Sedaghat),"System and methodology for development of a system architecture using optimization parameters", US Patent by United Sates Patent and Trademark Office (USPTO), Patent no. US 8,397,204, March 12, 2013. (Used/Cited in US Patent of Science & Technology Corporation, University of New Mexico).
  147. Anirban Sengupta (co-inventor: Reza Sedaghat),"System and Method for Development of System Architecture using optimization parameters", Canadian Patent by Canadian Intellectual Property Office (CIPO), Patent # CA2726091A1, June 21, 2012.
  148. Anirban Sengupta (co-inventor: Reza Sedaghat),"System and Methodology for Development of System Architecture", Canadian Patent by Canadian Intellectual Property Office (CIPO), Patent # CA2741253A1, Nov 27, 2012.


    149. National Patents

  149. Anirban Sengupta "Embedding Watermark based on Multi-Variable Signature Encoding at Behaviour Level for Reusable IP Core Protection", Patent 4466/MUM/2015, July 11, 2017.
  150. Anirban Sengupta, "Design Space Exploration Of An Optimized Hardware Trojan Detectable/Secured Datapath During High Level Synthesis", Patent#1666/MUM/2015, Â 2015
  151. Anirban Sengupta, "Design Space Exploration of Optimal Kc-Cycle Transient Fault Secured Datapath System with Intelligent Cut Insertion", Patent No. 63/MUM/2015, 2015.
  152. Anirban Sengupta "Design Space Exploration System and Method Thereof Using a Bacterial Foraging Optimization Mechanism", Patent No. 2440/MUM/2014, 2015 .
  153. Anirban Sengupta "Design Space Exploration of Optimal k-Cycle Transient Fault Tolerant Datapath Based on Multi-Objective Power-Performance Tradeoff", Patent No. 2456/MUM/2014, 2015.
  154. Anirban Sengupta "Method and System for Automatic Fault Recovery and True Output Extraction during High Level Synthesis", Patent No. 2478/MUM/2014, 2015.
  155. Anirban Sengupta "Improved Schedule Delay Estimation Process for Datapath during High Level Synthesis of Application Specific Processors", Patent No. 2482/MUM/2014, 2015, (Status: Published).


    156. PEER-REVIEWED CONFERENCE PROCEEDINGS

  156. Mahendra Rathor, Vipul Mishra, Anirban Sengupta, "Securing IP Cores in CE Systems using Key-driven Hash-chaining based Steganography", Proceedings of 10th IEEE International Conference on Consumer Electronics- Berlin (ICCE Berlin), Germany, Accepted, 2020

  157. Rahul Chaurasia, Anirban Sengupta,"Securing Reusable Hardware IP cores using Palmprint Biometric", Proceedings of 7th IEEE International Symposium on Smart Electronic Systems (formerly iNIS), India, Dec 2021
  158. Mahendra Rathor, Anirban Sengupta,"Signature Biometric based Authentication of IP Cores for Secure Electronic Systems", Proceedings of 7th IEEE International Symposium on Smart Electronic Systems (formerly iNIS), invited paper, India, Dec 2021
  159. Mahendra Rathor, Anirban Sengupta, "Obfuscating DSP Hardware Accelerators in CE Systems Using Pseudo Operations Mixing", Proceedings of 4th IEEE International Conference on Zooming Innovation in Consumer Electronics 2020 (ZINC 2020), Serbia, May 2020, pp. 218-221, doi: 10.1109/ZINC50678.2020.9161775
  160. Anirban Sengupta, Prajwal Chandra, Ranjith Kumar "Robust Digital Signature to Protect IP Core against Fraudulent Ownership and Cloning", Proceedings of 9th IEEE International Conference on Consumer Electronics - Berlin, Berlin, Sep 2019, pp. 122-124, doi: 10.1109/ICCE-Berlin47944.2019.9127238
  161. Anirban Sengupta, Gargi Gupta, Harshit Jalan "Hardware Steganography for IP Core Protection of Fault Secured DSP Cores", Proceedings of 9th IEEE International Conference on Consumer Electronics - Berlin, Berlin, Sep 2019, pp. 97 - 102, doi: 10.1109/ICCE-Berlin47944.2019.9127237
  162. Anirban Sengupta, Utkarsh Singh, Piyush Kalkute "Crypto based Multi-Variable Fingerprinting for Protecting DSP cores", Proceedings of 9th IEEE International Conference on Consumer Electronics - Berlin, Berlin, Sep 2019, pp. 1 - 6, doi: 10.1109/ICCE-Berlin47944.2019.9127235
  163. Anirban Sengupta, Mahendra Rathor "Enhanced Functional Obfuscation of DSP core using Flip-Flops and Combinational logic", Proceedings of 9th IEEE International Conference on Consumer Electronics - Berlin, Berlin, Sep 2019, pp. 7 - 11, doi: 10.1109/ICCE-Berlin47944.2019.9127236
  164. Dipanjan Roy, Anirban Sengupta "A Multi-Phase Intellectual Property Core Watermarking Approach during Architectural Synthesis", 24th Asia-South Pacific Design Automation Conference (ASP-DAC) SRF, Japan, Accepted, Jan 2019.
  165. Anirban Sengupta, Mahendra Rathor "Improved Delay Estimation Model for Loop Based DSP Cores", Proceedings of 37th IEEE International Conference on Consumer Electronics (ICCE), Las Vegas, USA, Jan 2019, pp. 1 - 4.
  166. Anirban Sengupta, Dipanjan Roy "Low-Overhead Highly Robust Embedded RTL Signature for DSP Core Protection: New Paradigm for Smart CE Design", Proceedings of 37th IEEE International Conference on Consumer Electronics (ICCE), Las Vegas, USA, Jan 2019, pp. 1- 6.
  167. Anirban Sengupta "Design Pruning of DSP Kernel for Multi Objective IP Core Architecture", Proceedings of 37th IEEE International Conference on Consumer Electronics (ICCE), Las Vegas, USA, Jan 2019, pp. 1 - 5.
  168. Anirban Sengupta "Message from the Conference Chair", Proceedings of 37th IEEE International Conference on Consumer Electronics (ICCE), Las Vegas, USA, Jan 2019.

  169. Anirban Sengupta, Deepak Kachave "Integrating Compiler Driven Transformation and Simulated Annealing based Floorplan for Optimized Transient Fault Tolerant DSP cores", International Symposium on Smart Electronic Systems (formerly iNIS), invited paper, Hyderabad, Dec 2018, pp. 17 - 20.
  170. Anirban Sengupta, Shubha Neema, Sri Harsha, Saraju P Mohanty, Mrinal Kanti Naskar "Obfuscation of Fault Secured DSP Design through Hybrid Transformation", Proceedings of 17th IEEE Computer Society Annual Symposium on VLSI (ISVLSI),, Hong Kong, 2018, pp. 732 - 737.
  171. Anirban Sengupta,, Saraju P. Mohanty "Functional Obfuscation of DSP cores using Robust Logic Locking and Encryption", Proceedings of 17th IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Hong Kong, 2018, pp. 709 - 713.
  172. Anirban Sengupta, Hui Zhao, Saraju P. Mohanty "Energy Efficient and Hardware Secured Architectures for Smart Electronics", Proceedings of 17th IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Accepted, Hong Kong, 2018.
  173. Anirban Sengupta, Jong Lee "Message from the Technical Program Chairs", Proceedings of 36th IEEE International Conference on Consumer Electronics (ICCE), Las Vegas, Jan 2018.
  174. Anirban Sengupta, MK Naskar "High Level Synthesis Methodology for Exploring Loop Unrolling Factor and Functional Datapath ", Proceedings of 2018 IEEE International Conference on Advanced Computation and Telecommunication, Bhopal, Accepted, Dec 2018.

  175. Anirban Sengupta, "Hardware Security of CE Devices: Threat Models and Defense against IP Trojans and IP Piracy", IEEE CE Society Distinguished Lecture, IEEE CE Society Educational Activities & Webinars, Sep 2017.
  176. Anirban Sengupta, "Anti-Piracy aware IP Chipset Design for CE Devices", IEEE CE Society Distinguished Lecture, IEEE CE Society Educational Activities & Webinars, Nov 2017.
  177. Anirban Sengupta, Sudeep Pasricha "Message from the Technical Program Chairs", Proceedings of 3rd IEEE International Symposium on Nanoelectronic and Information Systems (iNIS), Dec 2017.
  178. Anirban Sengupta, Dipanjan Roy "Multi-Phase Watermark for IP Core Protection", Proc. 36th IEEE International Conference on Consumer Electronics (ICCE) 2018, Las Vegas, Jan 2018, doi: 10.1109/ICCE.2018.8326058, pp. 1 - 3.
  179. Dipanjan Roy, Anirban Sengupta, "Reusable Intellectual Property Core Protection for Both Buyer and Seller", Proc. 36th IEEE International Conference on Consumer Electronics (ICCE) 2018, Las Vegas, Jan 2018, doi: 10.1109/ICCE.2018.8326059, pp. 1 - 3.
  180. Dipanjan Roy, Anirban Sengupta, "Low overhead symmetrical protection of reusable IP core using robust fingerprinting and watermarking during high level synthesis", Cyber Security Awareness Applied Research, IIT Kanpur- New York University, Accepted, Nov 2017.
  181. Deepak Kachave, Anirban Sengupta, "Forensic engineering for resolving ownership problem of reusable IP core generated during high level synthesis", Cyber Security Awareness Applied Research, IIT Kanpur- New York University, Accepted, Nov 2017.
  182. Saumya Bhadauria, Anirban Sengupta, Saraju P Mohanty "Methodology for Low Cost Hardware Trojan Security Aware Scheduling With Optimal Loop Unrolling Factor During High Level Synthesis " Cyber Security Awareness Applied Research, IIT Kanpur- New York University, Accepted, Nov 2017.
  183. Anirban Sengupta, "Reliability and Performance Aware SoC solutions for IoT Framework", IEEE International Symposium on Nanoelectronic and Information Systems (iNIS), June 2017.
  184. Anirban Sengupta, "Architecture-Level Energy, Security, and Reliability Solutions for CE Digital Hardware", 36th IEEE International Conference on Consumer Electronics (ICCE), Las Vegas, March 2017.
  185. Anirban Sengupta, Dipanjan Roy “Mathematical Validation of HWT Based Lossless Image Compression”, Proc. IEEE International Symposium on Nanoelectronic and Information Systems (iNIS), Dec 2017, pp. 20 - 22.
  186. Anirban Sengupta, Santosh Rathlavat, Mrinal Kanti Naskar “A Firefly Algorithm Driven Approach for High Level Synthesis”, Proc. IEEE International Symposium on Nanoelectronic and Information Systems (iNIS), Dec 2017, pp. 15 - 19.
  187. Deepak Kachave, Anirban Sengupta, Shubha Neema, Sri Harsha “Reliability and Threat analysis of NBTI Stress on DSP cores”, Proc. IEEE International Symposium on Nanoelectronic and Information Systems (iNIS), Dec 2017, pp. 11 - 14.
  188. Vipul Mishra, Anirban Sengupta, “Comprehensive Operation Chaining Based Schedule Delay Estimation during High Level Synthesis”, Proc. IEEE International Symposium on Nanoelectronic and Information Systems (iNIS), Dec 2017, pp. 66 - 68.

  189. Anirban Sengupta Madhavi Ganpatiraju, D. Das "Message from the Technical Program Chairs", Proc. IEEE Conference on Information Technology (ICIT), Dec 2016, pp. xiii - xiii.
  190. Deepak Kachave, Anirban Sengupta "Protecting Ownership of Reusable IP Core Generated during High Level Synthesis", Proceedings of IEEE International Symposium on Nanoelectronic and Information Systems (iNIS), Dec 2016, pp. 80 - 82.
  191. Anirban Sengupta, Saumya Bhadauria, Saraju Mohanty "Embedding Low Cost Optimal Watermark During High Level Synthesis for Reusable IP Core Protection", Proc. of 48th IEEE Int'l Symposium on Circuits & Systems (ISCAS), Montreal, May 2016, pp. 974 - 977.
  192. Anirban Sengupta, Deepak Kachave "Generating Multi-Cycle and Multiple Transient Fault Resilient Design during Physically Aware High Level Synthesis", Proc. 15th IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Pittsburgh, July 2016, pp. 75 - 80.
  193. Saumya Bhadauria, Anirban Sengupta, "A High Level Synthesis Approach for Exploring Low Cost kc-cycle Transient Fault Secured Solution", 21st Asia South Pacific-Design Automation Conference (ASP-DAC), Accepted, Jan 2016.

  194. Anirban Sengupta, Saumya Bhadauria "Untrusted Third Party Digital IP cores: Power-Delay Trade-off Driven Exploration of Hardware Trojan Secured Datapath during High Level Synthesis", 25th IEEE/ACM Great Lake Symposium on VLSI (GLSVLSI), Pennsylvania, May 2015, pp. 167 - 172 (DOUBLE BLIND REVIEW).
  195. Anirban Sengupta, Saumya Bhadauria, "User Power-Delay Budget Driven PSO Based Design Space Exploration of Optimal k-cycle Transient Fault Secured Datapath during High Level Synthesis", Proceedings of 16th IEEE International Symposium on Quality Electronic Design (ISQED), California, USA, March 2015, pp. 289 - 292 (DOUBLE BLIND REVIEW).
  196. Anirban Sengupta, Saumya Bhadauria, "Automated Design Space Exploration of Transient Fault Detectable Datapath Based on User Specified Power and Delay Constraints", Proceedings of 33rd VLSI - Design Automation & Test (VLSI - DAT) Taiwan, April 2015, pp. 1 - 4 (DOUBLE BLIND REVIEW).
  197. Anirban Sengupta, Vipul Kumar Mishra and Reza Sedaghat, "Exploration of Optimal Multi-Cycle Transient Fault Secured Datapath during High Level Synthesis based on User Area-Delay Budget", Proceedings of 28th IEEE Canadian Conference on Electrical & Computer Engineering (CCECE), Halifax, May 2015, pp. 69 - 74.
  198. Anirban Sengupta, Mrinal Kanti Naskar, "GA Driven Integrated Exploration of Loop Unrolling Factor and Datapath For Optimal Scheduling of CDFGs During High Level Synthesis", Proceedings of 28th IEEE Canadian Conference on Electrical & Computer Engineering (CCECE), Halifax, May 2015, pp. 75 - 80.
  199. Anirban Sengupta “Reliability and Security Aware RTL/System Design”, Special Session in IEEE iNIS 2015, Participants: Intel Corporation, Broadcom Corporation (USA), Pennsylvania State University (USA) and Indian Institute of Science, Proposal Accepted.
  200. Anirban Sengupta, Saumya Bhadauria, “Secure Information Processing during System level: Exploration of an Optimized Trojan Secured Datapath for CDFGs during HLS based on User Constraints”, Proceedings of IEEE iNIS 2015 Special Session, Dec 2015, pp. 1 - 6.

  201. Anirban Sengupta, Vipul Kumar Mishra, "Swarm Intelligence Driven Simultaneous Adaptive Exploration of Datapath and Loop Unrolling Factor during Area-Performance Tradeoff ", Proceedings of 13th IEEE Computer Society Annual International Symposium on VLSI (ISVLSI), Florida, USA, July 2014, pp. 106 112 (DOUBLE BLIND REVIEW).
  202. Anirban Sengupta, Vipul Kumar Mishra , "Integrated Particle Swarm Optimization (i-PSO): An Adaptive Design Space Exploration Framework for Power-Performance Tradeoff in Architectural Synthesis", Proceedings of IEEE 15th International Symposium on Quality Electronic Design (ISQED 2014), Santa Clara, California, USA, March 2014, pp.60 - 67 (DOUBLE BLIND REVIEW).
  203. Anirban Sengupta, Vipul Mishra, "'Automated Parallel Exploration of Datapath and Unrolling Factor in High Level Synthesis using Hyper-Dimensional Particle Swarm Encoding'", Proceedings of 27th IEEE Canadian Conference on Electrical and Computer Engineering, Toronto, May 2014, pp. 000069 - 000073.
  204. Anirban Sengupta, Saumya Bhadauria, "'Automated Exploration of Datapath in High Level Synthesis using Temperature Dependent Bacterial Foraging Optimization Algorithm'", Proceedings of 27th IEEE Canadian Conference on Electrical and Computer Engineering, Toronto, May 2014, pp. 68- 73.
  205. Anirban Sengupta, Vipul Mishra," Multidimensional Encoding Based Evolutionary Exploration Approach: Adaptive Methodology for Parametric Trade-offs in High Level Synthesis for Control flow Graphs", Proceedings of 3rd IEEE CALCON, IEEE Kolkata, Nov 2014, pp. 43 - 46.
  206. Vipul Mishra, Anirban Sengupta, "PSDSE: Particle Swarm Driven Design Space Exploration of Architecture and Unrolling Factors for Nested Loops in High Level Synthesis", Proceedings of 5th IEEE International Symposium on Electronic Design (ISED), Dec 2014, pp. pp. 10 - 14 (DOUBLE BLIND-REVIEW).
  207. Anirban Sengupta and Vipul Kumar Mishra, "Time Varying vs. Fixed Acceleration Coefficient PSO Driven Exploration during High Level Synthesis: Performance and Quality ", Proceedings of 13th IEEE International Conference on Information Technology, Dec 2014, pp. 281 - 286 (DOUBLE BLIND REVIEW).
  208. Anirban Sengupta and Saumya Bhadauria, "Error Masking of Transient Faults: Exploration of a Fault Tolerant Datapath Based on User Specified Power and Delay Budget", Proceedings of 13th IEEE International Conference on Information Technology, Dec 2014, pp. 345 - 350 (DOUBLE BLIND REVIEW).

  209. Anirban Sengupta, Vipul Kumar Mishra "Rapid Search of Pareto Fronts using D-logic Exploration during Multi-Objective Tradeoff of Computation Intensive Applications", Proceedings of IEEE 5th Asian Symposium on Quality Electronic Design (ASQED), Malaysia, August 2013, pp. 113-122.
  210. Vipul Mishra, Anirban Sengupta "Swarm Intelligence Driven Design Space Exploration: An Integrated Framework for Power-Performance Trade-off in Architectural Synthesis', Proceedings of 25th IEEE International Conference on Microelectronics (ICM 2013), Dec 2013, pp. 1 - 4.
  211. Anirban Sengupta, Vipul Mishra "D-logic Exploration: Rapid Search of Pareto Fronts during Architectural Synthesis of Custom Processors", Proceedings of IEEE International Conference on Advances in Computing, Communications and Informatics (ICACCI-2013), August 2013, Mysore, pp. 586 - 593.
  212. Anirban Sengupta "A Methodology for Self Correction Scheme Based Fast Multi Criterion Exploration and Architectural Synthesis of Data Dominated Applications", Proceedings of IEEE International Conference on Advances in Computing, Communications and Informatics (ICACCI-2013), August 2013, Mysore, pp.430 - 436.
  213. Anirban Sengupta "An Architecture Synthesis Tool for Rapid Multi-Objective Exploration and RTL Circuit Generation", ACM International Conference on Advances in Computing & Artificial Intelligence, Accepted, 2013.

  214. Anirban Sengupta, Reza Sedaghat ,"Priority Function Driven Design Space Exploration in High Level Synthesis Based on Power Gradient Technique", Accepted in Student Forum of 17th IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC 2012), Australia, pp: 25, 2012.

  215. Anirban Sengupta, Reza Sedaghat, "Integrated Scheduling, Allocation and Binding in High Level Synthesis using Multi Structure Genetic Algorithm based Design Space Exploration System", Proceedings of 12th IEEE/ACM International Symposium on Quality Electronic Design (ISQED 2011), Silicon Valley, California, USA, March 2011, pp. 486-494 (BLIND REVIEW).
  216. Anirban Sengupta, Reza Sedaghat, "A Hybrid Fuzzy Search Approach for Fast Design Space Exploration of Multi-Objective VLSI Systems", Accepted in the Student Forum of 16th IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC 2011), Japan, 2011,Paper ID: SF15.
  217. Anirban Sengupta, Reza Sedaghat "Integrated Scheduling, Allocation and Binding in High Level Synthesis for Performance-Area Tradeoff of Digital Media Applications", Proceedings of 24th IEEE Canadian Conference on Electrical and Computer Engineering (CCECE 2011), Canada, May 2011, pp. 533-537.
  218. Anirban Sengupta, Reza Sedaghat "Priority Function based Power Efficient Rapid Design Space Exploration of Scheduling and Module Selection in High Level Synthesis", Proceedings of 24th IEEE Canadian Conference on Electrical and Computer Engineering (CCECE 2011), Niagara, Canada, May 2011, pp. 538-543.
  219. Reza Sedaghat, Anirban Sengupta, "Power Gradient Based Design Space Exploration in High Level Synthesis for DSP Kernels", Proceedings of 23rd IEEE International Conference on Microelectronics (ICM), pp: 1 6, December 2011.
  220. Anirban Sengupta, Reza Sedaghat "Integrated Design Space Exploration Based on Power-Performance Trade-off using Genetic Algorithm", Proceedings of ACM International Conference on Advances in Computing and Artificial Intelligence, 2011, pp. 76-80.
  221. Reza Sedaghat, Anirban Sengupta, "Application Specific Processor vs. Microblaze Soft Core RISC Processor: FPGA Based Performance and CPR Analysis", Proceedings of ACM International Conference on Advances in Computing and Artificial Intelligence, 2011, pp.81-84.
  222. Summit Sehgal, Reza Sedaghat, Anirban Sengupta, "Automated Design Space Exploration for DSP Applications High Level Synthesis with Stability in Competition", Accepted for Publication, Proceedings of 2nd IEEE Latin American Symposium on Circuits and Systems (LASCAS), Columbia, February2011.

  223. Anirban Sengupta, Reza Sedaghat, Zhipeng Zeng, "Rapid Design Space Exploration for multi parametric optimization of VLSI designs", Proceedings of 2010 IEEE International Symposium on Circuits and Systems (ISCAS), Paris, France, pp: 3164-3167, June 2, 2010.
  224. Zhipeng Zeng, Reza Sedaghat, Anirban Sengupta, "A Framework for Fast Design Space Exploration using Fuzzy search for VLSI Computing Architectures", Proceedings of 2010 IEEE International Symposium on Circuits and Systems (ISCAS), Paris, France, 2010, pp: 3176-3179.
  225. Anirban Sengupta, Reza Sedaghat, "Accelerated Exploration of Cost-Performance Tradeoffs for Multi Objective VLSI designs", Proceedings of 22nd IEEE International Conference on Microelectronics (ICM), 2010, pp. 100-103.
  226. Anirban Sengupta, Reza Sedaghat "Rapid Exploration of Power-Delay Tradeoffs using Hybrid Priority Factor and Fuzzy Search", In Proceedings of 22nd IEEE International Conference on Microelectronics (ICM), Egypt,2010, pp. 355-358.
  227. Anirban Sengupta, Reza Sedaghat, "Fast Design Space Exploration for Multi Parametric Optimized VLSI and SoC Designs", Accepted in Student Forum of 15th IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC 2010), Taiwan, 2010,ID: 26.
  228. Anirban Sengupta, Reza Sedaghat, "A Study on Architecture Optimization of the RISC Processor used for System-on Chip (SoC) design", In Proceedings of Research Innovation Symposium, Ryerson University, Canada, 2010, pp: 31.
  229. Summit Sehgal, Reza Sedaghat, Anirban Sengupta, "Fault Monitoring Transformer Reliability ASIC Design based on Ringing Effect Signature Analyzer", Proceedings of Research Innovation Symposium, Ryerson University, Canada, 2010, pp: 32.

  230. Anirban Sengupta, Reza Sedaghat, Zhipeng Zeng, "Hardware Efficient Design of speed optimized Power stringent Application Specific Processor", Proceedings of 21st IEEE International Conference on Microelectronics (ICM), Morocco, pp: 167-170, December 22, 2009.
  231. Summit Sehgal, Reza Sedaghat, Anirban Sengupta, Zhipeng Zeng, "Multi Parametric Optimized Architectural Synthesis of an Application Specific Processor", Proceedings of 14th IEEE International CSI Computer Conference (CSICC), 2009, pp: 89-94.
  232. Zhipeng Zeng, Reza Sedaghat, Anirban Sengupta, "A Novel Framework of Optimizing Modular Computing Architecture for multi objective VLSI designs", Proceedings of 21st IEEE International Conference on Microelectronics (ICM), Morocco, 2009, pp: 322-325.

  233. Anirban Sengupta, Prasenjit Pal and S.K. Roy (Aug 1st & 2nd- 2008) "Problems Associated with CDMA Based Communication Systems Results and Discussions", Accepted for poster presentation in the IEEE and IEI, the National Conference on "Device, intelligent systems and communication& networking, Paper No: CN_27.


    234. THESIS/DISSERTATION

  234. Anirban Sengupta, "A Fast Design Space Exploration Based on Priority Factor for a Multi Parametric Optimized High Level Synthesis Design Flow", Master of Applied Science (M.A.Sc) Thesis, Ryerson University, Toronto, Canada, 2010,(Nominated for Governor Generals Gold Medal in Canada for the Master’s Thesis). Available at Ryerson University, Toronto Library.
  235. Anirban Sengupta, "Rapid and Efficient Multi Objective Design Space Exploration in High Level Synthesis of Computation Intensive Applications", Doctor of Philosophy (Ph.D.) Thesis, Ryerson University, Toronto, Canada, 2012.


    236. DOCTORAL THESIS SUPERVISED

  236. Vipul Kumar Mishra (Ph.D Student), Anirban Sengupta (Supervisor), "Multi-Objective Design Space Exploration in High Level Synthesis for Application Specific Computing", Doctor of Philosophy Thesis, Indian Institute of Technology Indore, 2015.
  237. Saumya Bhaduaria (Ph.D Student), Anirban Sengupta (Supervisor), "Low Cost Fault Reliability and Trojan Security Aware High Level Synthesis for Application Specific Datapath Processors", Doctor of Philosophy Thesis, Indian Institute of Technology Indore, 2016.
  238. Dipanjan Roy (Ph.D Student), Anirban Sengupta (Supervisor), "Hardware Security and IP Core Protection of CE Systems", Doctor of Philosophy Thesis, Indian Institute of Technology Indore, 2018.
  239. Deepak Kachave (Ph.D Student), Anirban Sengupta (Supervisor), "Transient Fault Reliability and Security of IP cores", Doctor of Philosophy Thesis, Indian Institute of Technology Indore, 2018.


    240. TECHNICAL REPORTS FOR INDUSTRY/IP OFFICE

  240. Anirban Sengupta, Reza Sedagha "Exploration Synthesizer: Design Automation Platform (DAP): Multi objective Design Space Exploration and Architectural Synthesis of Application kernels", No. of Pages: 14, Organization: Ryerson University (OPRAL Research Lab), MaRS Innovation, Aventis Consulting Group Inc and Venssa Technologies.
  241. Anirban Sengupta "Architectural Synthesis of Digital Systems (System Level Design)" , No. of pages: 39, Organization: Ryerson University (OPRAL Research Lab)
  242. Anirban Sengupta "An ASIC Implementation Design Flow of Function Specific Processor- System Level, Logic Level and layout level Synthesis" , No. of pages: 67, Organization: Ryerson University (OPRAL Research Lab)
  243. Anirban Sengupta "Performance Analysis of FPGA based ASP vs. Embedded Microblaze RISC Processor", No. of pages: 46, Organization: Ryerson University (OPRAL Research Lab),