Dr. Anirban Sengupta, Fellow IET, Fellow BCS (UK), Associate Professor, Computer Science and Engineering, Indian Institute of Technology (IIT) Indore
Professional Talks, Invited / Keynote Talks
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  1. Invited/Keynote Speaker in IEEE Consumer Electronics Society Chapter Bombay Section organized “Cybersecurity Conclave (CyVIT)”, Bhopal, April 5, 2019
  2. Panelist/Speaker in Cyber-security panel discussion in 37th IEEE International Conference on Consumer Electronics 2019, Las Vegas, USA
  3. Expert talk on “RTL based DSP core protection” in 37th IEEE International Conference on Consumer Electronics 2019, Las Vegas, USA
  4. Expert talk on “Improved Delay Estimation Model for DSP cores in CE Devices” in 37th IEEE International Conference on Consumer Electronics 2019, Las Vegas, USA
  5. Technical Speaker on “Hardware Security”, IEEE Consumer Electronics Society Chapter – Bombay Section on Jan 30, 2019, India
  6. Invited/Keynote Speaker on “IP Watermarking for DSP cores”, NIT Durgapur TEQIP workshop on Hardware Security on March 9, 2018 in India
  7. Invited/Keynote Speaker “Digital Forensic and Obfuscation for DSP cores”, NIT Durgapur TEQIP workshop on Hardware Security on March 10, 2018 in India
  8. Invited/Keynote Speaker on “Hardware Security”, Oriental University strong>IETE workshop on April 2018 in India
  9. Invited/Keynote Speaker on “Hardware/IoT Security” at Tripura Entrepreneurship and Technical Conclave, Torit Innovations Pvt Ltd, June 2, 2018 in India
  10. IEEE CE Society Distinguished Lecture/Keynote “Hardware Security of CE Devices: Threat Models and Defense against IP Trojans and IP Piracy”, IEEE professionals of Sydney, Tokyo audience, Sep 9, 2017
  11. Expert Talk on "Reliability and Performance Aware SoC solutions for IoT Framework" in IEEE International Symposium on Nanoelectronic and Information Systems (iNIS) on Dec 2017
  12. Invited Talk on “Watermarking of IP core” in NTU Singapore on June 2016
  13. Expert Talk on “Exploration of Optimal Multi-Cycle Transient Fault Secured Datapath during High Level Synthesis based on User Area-Delay Budget” in 28th IEEE Canadian Conference on Electrical and Computer Engineering, Halifax on May 2015
  14. Expert Talk on “GA Driven Integrated Exploration of Loop Unrolling Factor and Datapath For Optimal Scheduling of CDFGs During High Level Synthesis” in 28th IEEE Canadian Conference on Electrical and Computer Engineering, Halifax on May 2015
  15. Expert Talk on “Reliability and Security Aware RTL/System Design” in IEEE International Symposium on Nanoelectronic and Information Systems (iNIS) on Dec 2015
  16. Expert Talk on “Automated Exploration of Datapath in High Level Synthesis using Temperature Dependent Bacterial Foraging Optimization Algorithm” in 27th IEEE Canadian Conference on Electrical and Computer Engineering, Toronto on May 6, 2014
  17. Expert Talk on “Automated Parallel Exploration of Datapath and Unrolling Factor in High Level Synthesis using Hyper-Dimensional Particle Swarm Encoding” in 27th IEEE Canadian Conference on Electrical and Computer Engineering, Toronto on May 6, 2014
  18. Expert Talk on “Data path unrolling schemes during HLS” in Communication Systems and Implementation workshop by IIT-I and MCTE on April 19, 2014
  19. Expert Talk on “Rapid Search of Pareto Fronts using D-logic Exploration during Multi-Objective Tradeoff of Computation Intensive Applications” in the 5th IEEE Asia Symposium on Quality Electronic Design (ASQED 2013) in Malaysia on August 27, 2013
  20. Talk on “Integrated Scheduling, Allocation and Binding in High Level Synthesis using Multi Structure Genetic Algorithm based Design Space Exploration System” in the 12th IEEE/ACM International Symposium on Quality Electronic Design (ISQED 2011) in Silicon Valley, California, USA on March 15, 2011
  21. Talk on “Exploration Synthesizer: Design Automation Platform (DAP): Multi objective Design Space Exploration and Architectural Synthesis of Application kernels” to Aventis Consulting Group Inc and MaRS Innovation, Toronto, Ontario (Canada) on September 6, 2011
  22. Talk on “Hardware Efficient Design of speed optimized Power stringent Application Specific Processor” in the session ‘Digital Systems Design’ of the IEEE 21st International Conference on Microelectronics (ICM) on December 21, 2009 at Morocco
  23. Talk on “Soft error injection using Advanced Switch-level models for Combinational logic in Nanometre Technologies” in the IEEE 21st International Conference on Microelectronics (ICM) on December 22, 2009 at Morocco
  24. Talk on “Data pre-fetching Mechanisms for High Performance Computer System Design” in Graduate Research Seminar during Master of Applied Science degree at Ryerson University, Canada, 2009
  25. Talk on “Rapid Design Space Exploration for multi parametric optimization of VLSI designs” in IEEE International Symposium on Circuits and Systems (ISCAS) in Paris, France on June 2nd, 2010
  26. Talk on “A Framework for Fast Design Space Exploration using Fuzzy search for VLSI Computing Architectures” in IEEE International Symposium on Circuits and Systems (ISCAS) in Paris, France on June 2nd, 2010
  27. Talk on “High Level Synthesis Design Flow of Multi-Objective Parametric EDA Tools” in the seminar series at Computer Aided Design Laboratory (CADL), Center of Electronic Design Technology at Indian Institute of Science (IISc), India on April 13, 2012
  28. Talk on “Rapid Design Space Exploration of DSP Kernels based on multi parametric objective” in the seminar series at Computer Aided Design Laboratory (CADL), Center of Electronic Design Technology at Indian Institute of Science (IISc), India on April 16, 2012
  29. Talk on “Priority Function Driven Design Space Exploration in High Level Synthesis Based on Power Gradient Technique” in the seminar series at Computer Aided Design Laboratory (CADL), Center of Electronic Design Technology at Indian Institute of Science (IISc), India on April 17, 2012
  30. Talk on “A Framework for Fast Design Space Exploration using Fuzzy search for VLSI Computing Architectures” in the seminar series at Computer Aided Design Laboratory (CADL), Center of Electronic Design Technology at Indian Institute of Science (IISc), India on April 20, 2012
  31. Talk on "Integrated Design Space Exploration Based on Power-Performance Trade-off using Multi Structure Genetic Algorithm” in the seminar series at Computer Aided Design Laboratory (CADL), Center of Electronic Design Technology at Indian Institute of Science (IISc), India on April 20, 2012